1. Field of the Invention
The present invention relates to a class of electronic circuits (e.g., integrated circuits) in which an internal control signal is generated (to switch components of the circuit between an "active" and a "standby" mode) in response to a transition in an external control signal (commonly known as a "chip enable" or "CE" signal) from an external device. In accord with preferred embodiments of the invention, a memory chip (an integrated circuit) generates two internal standby signals (one delayed with respect to the other) in response to an external standby command (a transition in a chip enable signal), at least one component circuit of the chip (e.g., an address buffer) receives the delayed internal standby signal, and at least one other component circuit of the chip receives the non-delayed internal standby signal.
2. Description of Related Art
For convenience, the following notation is used in the description of the drawings (FIGS. 1-7). The symbol -N (where "N" is any signal name) is used in the specification to denote a signal identified by the corresponding symbol N in the drawings. For example, the signal identified as "CE" in FIG. 1 is identified in the specification as "-CE."
The description of FIGS. 1-7 assumes that each signal -N represents a logical "1" when its value (e.g., voltage level) is low (below a threshold), and represents a logical "0" when its value is high (above the threshold). Of course, it is within the scope of the invention to employ circuitry implementing the logical functions described with signals having the opposite polarities.
Many conventional integrated circuits (such as memory circuits) operate in either a "standby" mode in which all but essential component circuits are shut off to save power, or an "active" (or "enabled") mode in which all component circuits are enabled to perform their intended functions. Typically, such circuits have a pad (known as a "chip enable," "CE," or "-CE" pad) to which an external device asserts a "chip enable" command signal. Such a command signal is a digital signal whose level indicates either that the integrated circuit should operate in a standby mode, or that the integrated circuit should operate in an active mode.
For example, FIG. 1 is a simplified block diagram of a conventional CMOS memory circuit (an integrated circuit) which includes the following components: address buffers A0 through Ap, chip enable buffer 10, address decoder circuits 12 and 14, memory array 16, sense amplifier 18, and output buffer 20. Each of the storage locations of memory array circuit 16 is indexed by a row index (an "X" index output from decoder circuit 12) and a column index (a "Y" index output from decoder circuit 14).
In the FIG. 1 circuit, each of address buffers A0 through Ap is connected to a different address bit pad, and each receives (from an external device) a different one of address bit signals X0 through Xn and Y0 through Ym. Each of address buffers A0 through Ap is enabled by chip enable signal -CEint supplied thereto from buffer 10.
An external device asserts command signal -CE to chip enable pad 8 of FIG. 1. Chip enable buffer circuit 10 receives signal -CE, and generates chip enable signal -CEint in response to signal -CE as follows:
when -CE is low (its value represents a logical "1"), -CEint is low (and -CEint serves to enable all component circuits, such as address buffers A0 through Ap, to which circuit 10 asserts it); and
when -CE is high, -CEint is high (and -CEint serves to put into a standby mode all component circuits to which circuit 10 asserts it).
In the standby mode (in response to a high value of -CEint), address buffers A0 through Ap are disabled and consume much less power than when enabled by a low value of -CEint.
In the active mode (when enabled by a low value of -CEint), address buffers A0 through Ap operate as follows. Each of address buffers A0 through An asserts one of bits X0-Xn to address decoder circuit 12, and each of address buffers An+1 through Ap asserts one of bits Y0-Ym to address decoder circuit 14. In response to these address bits, circuit 12 asserts a row address to memory array 16 and circuit 14 asserts a column address to memory array 16. In response to a memory access command (a read or write command supplied to array 16 from control circuitry not shown in FIG. 1), data is read from or written to the storage location of array 16 determined by the row and column address. When the memory access command is a "read" command, array 16 outputs to sense amplifier 18 a data signal indicative of the data value stored in the storage location determined by the row and column address, amplifier 18 asserts a corresponding amplified data signal to output buffer 20, and output buffer asserts a corresponding "OUTPUT DATA" signal at an external pin of the FIG. 1 circuit.
FIG. 2 is a typical implementation of one of the address buffers (A0 through Ap) of FIG. 1. The address buffer of FIG. 2 receives an address bit signal (one of X0-Xn and Y0-Ym) at pad 30, and it receives chip enable signal -CEint at node 32. The FIG. 2 circuit includes P-channel MOS transistor P2, N-channel MOS transistor N2, and a CMOS inverter comprising P-channel MOS transistor P1 and N-channel MOS transistor N1. The source of P2 is connected to supply voltage V.sub.cc, the drain of P2 is connected to the source of P1, the drain of P1 is connected to the source of N1, and the drain of N1 is connected to ground. The gate of each of transistors P2 and N2 is connected to node 32, so that when -CEint is low (i.e., the FIG. 2 circuit is in an active mode) transistor P2 is "on" and transistor N2 is "off." In the "active" mode, the FIG. 2 circuit responds to TTL level voltages at pad 30 (each determining an address bit) as follows. When pad 30 is low, transistor P1 is "on" and transistor N1 is "off," so that the voltage level of output node 34 is pulled "high" by V.sub.cc. When pad 30 is high, transistor P1 is "off" and transistor N1 is "on," so that output node 34 is pulled "low." In its active mode, the address buffer shown in FIG. 2 typically draws DC current on the order of 50-100 microamps. In typical implementations of FIG. 1 including eighteen to twenty address buffers, when the address buffers are active, the address buffers (and the other circuitry operating in response to the active address buffers) will draw a total of on the order of 20-40 milliamps. If there were twenty memory chips (of the FIG. 1 type) on a single board, the standby mode could thus reduce the board's power requirements by several hundreds of milliamps.
When -CEint is high (i.e., when the FIG. 2 circuit is in its standby mode) transistor P2 is "off" and transistor N2 is "on." In this standby mode, output node 34 remains "low" regardless of the level of input pad 30, and the FIG. 2 circuit consumes no power.
FIG. 3 is a typical implementation of chip enable buffer 10 of FIG. 1. The chip enable buffer of FIG. 3 receives the chip enable signal "-CE" at input pin 48 (connected to pad 8 shown in FIG. 1) of TTL buffer 50, and optionally also receives a "-Power Up" signal at input pin 49 of buffer 50. The function of "-Power Up" is to activate the FIG. 3 circuit when it is in a "deep power down" mode. The latter mode is different from the above-mentioned "standby mode" (triggered by a "high" value of chip enable signal -CE) in that power is disconnected from more components of the FIG. 1 circuit in deep power down than in standby, and in that different external devices supply signals "-CE" and "-Power Up." Because the FIG. 3 circuit responds identically to identical transitions of signals -Power Up and -CE, operation of the FIG. 3 system will be further described with reference to signal -CE only.
The FIG. 3 circuit is designed to minimize inherent delays in generating signal -CEint. This is important because the address buffers (A0 through Ap) are some of the first elements that need to be powered up by a low value of -CEint (in response to a low value of -CE), so that delay in generating a low-going transition of -CEint is directly in the speed path of the FIG. 1 chip. The FIG. 3 circuit must also be designed so that the signal -CEint has sufficient current drive capability to drive the necessary load. These design requirements are met by connecting the output of buffer 50 (an inverting amplifier) to a sequence of buffers (inverters) 52, 54, 56, 58, and 60 connected in series. The size of each inverter (52, 54, 56, 58, and 60) in this sequence is such that the final inverter (60) outputs a signal -CEint adequate to drive the load. The ratio of the sizes of successive inverters in the sequence is selected to minimize the delay in asserting the output signal -CEint (each inverter in the sequence typically has a larger size than the previous inverter in the sequence), so that the final buffer outputs signal -CEint with sufficiently short delay time.
The gate of P-channel MOS transistor 62 is connected to the output of inverter 52. In response to a low-going edge of -CE (triggering a standby-to-active transition of the FIG. 1 circuit), the output of inverter 52 also undergoes a high-to-low voltage transition, thus switching transistor 62 "on." More specifically, once the trip voltage of inverter 52 is reached, the output of inverter 52 will go low. The flow voltage at the output of inverter 52 is fed back to transistor 62 and will cause transistor 62 to turn on thereby causing the voltage at the input to inverter 52 to be pulled up even higher. This positive feedback provides hysteresis, so that the magnitude of the low-to-high transition applied to pin 48 that is necessary to trigger an active-to-standby mode transition of the FIG. 1 circuit, is reduced. Thus, once the FIG. 1 circuit has entered the active mode, a slight increase in the low voltage applied to pin 48 (due to noise or the like) will not cause the FIG. 1 circuit to exit the active mode.
In response to a high-going edge of -CE (triggering an active-to-standby transition of the FIG. 1 circuit), the output of inverter 52 also undergoes a low-to-high voltage transition, thus switching transistor 62 "off."
A significant problem resulting during operation of the conventional FIG. 1 circuit will next be described in connection with the timing diagram of FIG. 4. This problem is that a longer time (denoted T.sub.CE) is required for a memory access when the FIG. 1 circuit is in its standby mode, than the time (denoted T.sub.AA) required for a memory access when the FIG. 1 circuit is in its active mode (enabled by a low value of signals -CE and -CEint).
FIG. 4 assumes that the FIG. 1 circuit is active (-CE is low) from time t.sub.0 through time t.sub.4, and is in a "read" mode (in which it outputs a stored data value from memory 16 in response to an address received at address buffers A0-Ap). At time t.sub.0, the circuit receives a first address (a first set of values of address signals X0-Xn and Y0-Ym) at its address buffers. Due to the time inherently required for responding to this address in address buffers A0-Ap, decoders 12 and 14, memory array circuit 16 (which can be an array of flash memory cells), sense amplifier 18 and output buffer 20, it is not until time t.sub.1 that the output of buffer 20 represents valid data. Similarly, in response to a second address asserted at time t.sub.2, it is not until time t.sub.3 that the output of buffer 20 represents a second valid quantity of data. The time delay, (t.sub.1 -t.sub.0)=(t.sub.3 -t.sub.2)=T.sub.AA (known as "address access" time), is typically 60 ns (in a CMOS integrated circuit implementation of FIG. 1 in which memory array 16 is an array of flash memory cells).
FIG. 4 assumes that the circuit enters a standby mode (-CE goes high) at time t.sub.4. Then, at time t.sub.5, it receives a third address at its address buffers, and -CE goes low. Due to the time (T.sub.x) inherently required by buffer 10 to respond to this high-to-low transition of signal -CE by causing a corresponding high-to-low transition of its output signal -CEint, it is not until time t.sub.6 that the address buffers are enabled (and thus able to recognize and respond to the "third address" asserted thereto). An additional address access time T.sub.AA is then required (from time t.sub.6 to time t.sub.7) before the output of buffer 20 represents a third valid quantity of data (the data indexed by the third address). Buffer 20 becomes disabled (shortly after time t.sub.4) in response to the low-to-high transition of -CE at time t.sub.4, and thus its output represents invalid data from the time it becomes disabled until time t.sub.7.
The time delay T.sub.x is typically 5 ns to 10 ns (in an integrated circuit implementation of FIG. 2). Thus, the time delay, (t.sub.7 -t.sub.5)=T.sub.AA +T.sub.X =T.sub.CE (known as "chip enable access" time), is typically 65 ns to 70 ns (in the above-mentioned CMOS integrated circuit implementation of FIG. 1 in which memory array 16 is an array of flash memory cells).
We denote as the "T.sub.CE effect" the problem of longer response time required for responding to a command (such as a "read" command to a memory chip) from a "standby" mode than from an "active" mode. Of course, memory circuits other than those of the type shown in FIG. 1, and circuits other than memory circuits, are subject to the T.sub.CE effect.
A circuit embodying the present invention is not subject to the T.sub.CE effect (to a selected degree), and thus can respond with decreased average response time to a sequence of commands (e.g., memory access commands, in memory circuit embodiments of the invention).